Conventionally, there is a semiconductor device which has a multilayer wiring structure. In such a semiconductor device, lower layer wirings and upper layer wirings are electrically connected through contact holes that are formed in an interlayer insulating film.
FIG. 13 is a diagram for explaining a wiring structure of such a semiconductor device. FIG. 13(a) is a plan view, and FIG. 13(b) is a cross-sectional view along a line XIIIb--XIIIb shown in FIG. 13(a). In the figure, reference numeral 250 designates a wiring structure that is formed on a silicon substrate 5. This wiring structure 250 has a lower layer wiring (first wiring) 1 that extends along a first direction D1 and has a wiring width direction in a second direction D2 perpendicular to the first direction D1, and upper layer wirings (second wirings) 2a and 2b that extend along the first direction D1 and are electrically connected to the lower layer wiring 1.
More specifically, the lower layer wiring 1 is formed on the silicon substrate 5 via an underlying insulating film 6, and the lower layer wiring 1 is covered with an interlayer insulating film 7. Further, the upper layer wirings (second wirings) 2a and 2b are formed on the interlayer insulating film 7. An end portion 2a.sub.1 of the upper layer wiring 2a is connected to an end portion 1a of the lower layer wiring 1 through a contact hole 7a that is formed in the interlayer insulating film 7. An end portion 2b.sub.1 of the upper layer wiring 2b is connected to the other end portion 1b of the lower layer wiring 1 through a contact hole 7b that is formed in the interlayer insulating film 7.
As a composing material of the upper layer wirings 2a and 2b, a metallic material of a low melting point, such as aluminum, which is relatively low-priced is used. As a composing material of the lower layer wiring 1, a metallic material of a high melting point, such as platinum and tungsten, is used, because various high temperature processing is usually performed after formation of the lower layer wiring.
By the way, as the conventional semiconductor devices having multilayer wiring structures described above, there have been developed various circuits from relatively small-sized integrated circuits mounting, for example, an amplifier circuit, an oscillating circuit, a power supply circuit and the like, to relatively large-sized integrated circuits, such as a microprocessor and a memory device. Especially in recent years, as a kind of non-volatile memory device, a ferroelectric memory device with ferroelectric capacitors as capacitors constituting memory cells has been contrived.
The ferroelectric capacitor consists of a pair of electrodes opposite to each other, and a dielectric layer comprising a ferroelectric material and sandwiched between both electrodes, and has the hysteresis characteristic as a relationship between a voltage applied between the both electrodes and polarizability of the ferroelectric material. That is, the ferroelectric capacitor has a construction in which even when the electric field (applied voltage) is zero, a remanence of a polarity in accordance with the hysteresis of voltage application remains in the ferroelectric layer. In the ferroelectric memory device non-volatility of the storage data is realized by representing storage data by the remanence of the ferroelectric capacitor.
FIGS. 14 and 15 are diagrams for explaining a conventional ferroelectric memory device. FIG. 14 is a plan view illustrating a memory cell array in the ferroelectric memory device. FIG. 15(a) is a cross-sectional view of a part along a line XVa--XVa shown in FIG. 14, FIG. 15(b) is a cross-sectional view of a part along a line XVb--XVb shown in FIG. 14, and FIG. 15(c) is a cross-sectional view of a part along a line XVc--XVc shown in FIG. 14.
In the figures, reference numeral 200 designates a memory cell array constituting a ferroelectric memory device. On a silicon substrate 201, a plurality of transistor regions 220a are arranged in a first direction D1, and an insulating film 202 for element isolation is formed on a portion of the silicon substrate 201, except the transistor regions 220a.
On both sides of the transistor regions 220a in a line along the first direction D1, lower electrodes (first electrodes) 211 are formed as cell plate electrodes on the insulating film 202 for element isolation via first interlayer insulating films 203. The lower electrode 211 comprises a metallic material of a high melting point, such as platinum, iridium, tungsten and titanium, and has a stripe-shaped plan configuration extending along the first direction D1. On surfaces of the lower electrodes 211, ferroelectric layers 213 are formed.
On the ferroelectric layers 213 on the surfaces of the lower electrodes 211, upper electrodes (second electrodes) 212 comprising a metallic material of a high melting point, such as platinum, iridium, tungsten and titanium, are formed corresponding to the respective transistor regions 220a. That is, on the ferroelectric layers 213, the plurality of upper electrodes 212 are arranged along the first direction D1. A plan shape of each upper electrode 212 is a rectangular shape having the first direction D1 as a longitudinal direction. In addition, as is known from FIG. 14, the area of each upper electrode 212 is smaller than that of the lower electrode 211. Here, the lower electrode 211, the upper electrodes 212, and the ferroelectric layer 213 located between these electrodes constitute ferroelectric capacitors 210. The surfaces of the ferroelectric layers 213 and the surfaces of the upper electrodes 211 are covered with second interlayer insulating films 204.
In this case, in order to reduce variations in the characteristics of the ferroelectric capacitors 210, i.e., variations in polarizability of the ferroelectric layers, and make changes in the characteristic, i.e., changes in polarizability with passage of time, less, the distances between the adjacent upper electrodes 212 and the areas of the upper electrodes 212 on the lower electrode 211 are set, considering thermal stresses generated in the lower electrode 211 and the like.
Between the pair of lower electrodes 211 that sandwich the transistor regions 220a opposing to each other, a pair of word lines (second wirings) 223a and 223b comprising polysilicon is disposed so as to straddle over the plurality of transistor regions 220a arranged in a line. A source diffusion region 222 and drain diffusion regions 221 of a memory transistor 220 constituting a memory cell are formed on both sides of the word lines 223a and 223b in each transistor region 220a. Portions of the word lines 223a and 223b located above each transistor region 220a constitute gate electrodes of the memory transistor 220, and are located on the substrate surface via gate insulating films 202a. The surfaces of the diffusion regions 221 and 222 and the word lines 223a and 223b are covered with the first and second interlayer insulating films 203 and 204. In FIG. 14, these interlayer insulating films are not shown.
The source diffusion region 222 located between the pair of word lines 223a and 223b in each transistor region 220a is connected to a bit line 233b extending along a second direction D2 perpendicular to the first direction D1, through a contact hole 205b formed in the first and second interlayer insulating films 203 and 204. The drain diffusion regions 221 located outside the opposite word lines 223a and 223b in each transistor region 220a are electrically connected to the upper electrodes 212 via connecting wirings 233a. That is, one end of the connecting wiring 233a is connected to the upper electrode 212 through a contact hole 204a formed in the second interlayer insulating film 204. The other end of the connecting wiring 233a is connected to the drain diffusion region 221 through a contact hole 205a formed in the first and second interlayer insulating films 203 and 204.
Both end portions 211a and 211b of the lower electrode 211 are connected to upper layer wirings 206a and 206b through contact holes 208a and 208b that are formed in the interlayer insulating films 203 and 204, respectively. The ferroelectric layer 213 formed on the surface of the lower electrode 211 is removed at portions of the lower electrode 211 that are connected to the upper layer wirings 206a and 206b.
The lower electrodes 211 and the ferroelectric layers 213 are formed by successively forming films of a metallic material, such as titanium and platinum, and a ferroelectric material on the interlayer insulating film 203 and patterning the films. The upper electrodes 212 are formed by forming a film of a metallic material, such as titanium and platinum, on the ferroelectric layer 213 and patterning this film. The bit lines 233b, the connecting wirings 233a, and the upper layer wirings 206a and 206b are formed by patterning a metallic film, such as aluminum, formed on the interlayer insulating film 204. The word lines 223a and 223b are formed by patterning a polysilicon film that is formed on the gate insulating films 202a and the insulating film 202 for element isolation.
The first interlayer insulating film 203 comprises an insulating material, such as NSG (oxide silicon based) and BPSG (boron, phosphine doped oxide silicon), and the second interlayer insulating film 204 comprises, for example, PSG (phosphine doped oxide silicon).
As the ferroelectric material composing the ferroelectric layer 213 of the ferroelectric capacitors, KNO.sub.3, PbLa.sub.2 O.sub.3 --ZrO.sub.2 --TiO.sub.2, PbTiO.sub.3 --PbZrO.sub.3 or the like has been known. In addition, PCT International Publication WO 93/12542 also discloses a ferroelectric material that has extremely low fatigueness as compared with PbTiO.sub.3 --PbZrO.sub.3, being suitable for a ferroelectric memory device.
Also in such a ferroelectric memory device, the wiring structure 250 shown in FIGS. 13(a) and 13(b) is employed in peripheral circuits, except a memory cell array. When the lower layer wiring 1 of the wiring structure 250 comprises the same composing material as the lower electrode 211 of the memory cell array 200 described above, for example, platinum, seeing from the viewpoint of simplification of wafer processes, as shown in FIG. 13(c), it is more advantageous that a ferroelectric material layer 3 which is to be a dielectric layer of the ferroelectric capacitor remains on a region of the surface of the lower layer wiring 1, except portions connected to the upper layer wirings 2a and 2b.
The operation will be described briefly.
In the ferroelectric memory device with the construction as described above, when, for example, the word line 223a is selected and subsequently, one of the lower electrodes 211 (for example, the uppermost lower electrode shown in FIG. 14) is driven, thereby making the voltage level thereof the level corresponding to the logical voltage "H", storage data of the ferroelectric capacitors 210 formed on this lower electrode are read out onto the respective bit lines 233b through the connecting wirings 233a and the transistors 220. The storage data read out onto the respective bit lines 233b are amplified by sense amplifiers (not shown) to be output to the outside of the ferroelectric memory device. Thereafter, the voltage level of the lower electrode 211 is made a level corresponding to the logical voltage "L" to make the word line 223a the unselected state, thereby completing the reading out.
However, in such a device in which the lower layer wiring 1 in the multilayer wiring structure comprises a conductive material having a larger thermal expansion coefficient, such as platinum, as the conventional semiconductor device shown in FIG. 13, the lower layer wiring 1 that is formed by high temperature processing contracts at normal temperature. Therefore, great tensile force is applied to the upper layer wirings 2a and 2b connected to this wiring. Especially when the plan shape of the lower layer wiring 1 is a slender shape, the thermal stresses of the lower layer wiring 1 that are applied to the portions connected to the upper layer wirings 2a and 2b become extremely large, so that there may be produced breaking of the connection portions of the lower layer wiring 1 and the upper layer wirings 2a and 2b, and the upper layer wirings 2a and 2b may break. As described above, there is a problem in that the thermal stresses generated in the lower layer wiring 1 become obstacles to high reliability of the semiconductor device.
Also in the conventional ferroelectric memory device with ferroelectric capacitors shown in FIGS. 14 and 15, since the lower electrode 211 as a cell plate electrode has a stripe-shaped plan, the thermal stresses of the lower electrode 211 that are applied to the portions connected to the upper layer wirings 206a and 206b become extremely large, so that there may be produced breaking of the connection portions of the lower electrode 211 and the upper layer wirings 206a and 206b, and the upper layer wirings 206a and 206b may break. Further, in addition to the deterioration of reliability due to the breaking as described above, the thermal stresses of the lower electrode 211 affect the ferroelectric layer 213 thereon, thereby causing variations in the characteristics and deterioration of the characteristics of the ferroelectric capacitors. As a result, there is another problem in that the performance and reliability of the ferroelectric memory device are deteriorated.
The present invention is directed to solving the above-described conventional problems, and has an object to provide a semiconductor device in which the influences by stresses generated in a wiring or an electrode can be reduced, thereby suppressing breaking at wirings and an electrode, and variations in characteristics and characteristic deterioration of ferroelectric capacitors that are disposed on the electrode.